03063Z105KAT4A [KYOCERA AVX]

Low Inductance Capacitors;
03063Z105KAT4A
型号: 03063Z105KAT4A
厂家: KYOCERA AVX    KYOCERA AVX
描述:

Low Inductance Capacitors

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Low Inductance Capacitors  
Introduction  
The signal integrity characteristics of a Power Delivery  
Network (PDN) are becoming critical aspects of board level  
and semiconductor package designs due to higher operating  
frequencies, larger power demands, and the ever shrinking  
lower and upper voltage limits around low operating voltages.  
These power system challenges are coming from mainstream  
designs with operating frequencies of 300MHz or greater,  
modest ICs with power demand of 15 watts or more, and  
operating voltages below 3 volts.  
capacitor, one resistor, and one inductor. The RLC values in  
this model are commonly referred to as equivalent series  
capacitance (ESC), equivalent series resistance (ESR), and  
equivalent series inductance (ESL).  
The ESL of a capacitor determines the speed of energy  
transfer to a load. The lower the ESL of a capacitor, the faster  
that energy can be transferred to a load. Historically, there  
has been a tradeoff between energy storage (capacitance)  
and inductance (speed of energy delivery). Low ESL devices  
typically have low capacitance. Likewise, higher capacitance  
devices typically have higher ESLs. This tradeoff between  
ESL (speed of energy delivery) and capacitance (energy  
storage) drives the PDN design topology that places the  
fastest low ESL capacitors as close to the load as possible.  
Low Inductance MLCCs are found on semiconductor  
packages and on boards as close as possible to the load.  
The classic PDN topology is comprised of a series of  
capacitor stages. Figure 1 is an example of this architecture  
with multiple capacitor stages.  
An ideal capacitor can transfer all its stored energy to a load  
instantly. A real capacitor has parasitics that prevent  
instantaneous transfer of a capacitors stored energy. The  
true nature of a capacitor can be modeled as an RLC  
equivalent circuit. For most simulation purposes, it is possible  
to model the characteristics of a real capacitor with one  
Slowest Capacitors  
Fastest Capacitors  
Semiconductor Product  
VR  
Bulk  
Board-Level  
Package-Level  
Die-Level  
Low Inductance Decoupling Capacitors  
Figure 1 Classic Power Delivery Network (PDN) Architecture  
LOW INDUCTANCE CHIP CAPACITORS  
INTERDIGITATED CAPACITORS  
The key physical characteristic determining equivalent series  
inductance (ESL) of a capacitor is the size of the current loop  
it creates. The smaller the current loop, the lower the ESL. A  
standard surface mount MLCC is rectangular in shape with  
electrical terminations on its shorter sides. A Low Inductance  
Chip Capacitor (LICC) sometimes referred to as Reverse  
Geometry Capacitor (RGC) has its terminations on the longer  
side of its rectangular shape.  
The size of a current loop has the greatest impact on the ESL  
characteristics of a surface mount capacitor. There is a  
secondary method for decreasing the ESL of a capacitor.  
This secondary method uses adjacent opposing current  
loops to reduce ESL. The InterDigitated Capacitor (IDC)  
utilizes both primary and secondary methods of reducing  
inductance. The IDC architecture shrinks the distance  
between terminations to minimize the current loop size, then  
further reduces inductance by creating adjacent opposing  
current loops.  
When the distance between terminations is reduced, the size  
of the current loop is reduced. Since the size of the current  
loop is the primary driver of inductance, an 0306 with a  
smaller current loop has significantly lower ESL then an 0603.  
The reduction in ESL varies by EIA size, however, ESL is  
typically reduced 60% or more with an LICC versus a  
standard MLCC.  
An IDC is one single capacitor with an internal structure that  
has been optimized for low ESL. Similar to standard MLCC  
versus LICCs, the reduction in ESL varies by EIA case size.  
Typically, for the same EIA size, an IDC delivers an ESL that  
is at least 80% lower than an MLCC.  
59  
Low Inductance Capacitors  
Introduction  
LAND GRID ARRAY (LGA) CAPACITORS  
LOW INDUCTANCE CHIP ARRAYS (LICA®)  
Land Grid Array (LGA) capacitors are based on the first Low  
ESL MLCC technology created to specifically address the  
design needs of current day Power Delivery Networks (PDNs).  
This is the 3rd low inductance capacitor technology  
developed by AVX. LGA technology provides engineers with  
new options. The LGA internal structure and manufacturing  
technology eliminates the historic need for a device to be  
physically small to create small current loops to minimize  
inductance.  
The LICA® product family is the result of a joint development  
effort between AVX and IBM to develop a high performance  
MLCC family of decoupling capacitors. LICA was introduced  
in the 1980s and remains the leading choice of designers in  
high performance semiconductor packages and high  
reliability board level decoupling applications.  
LICA® products are used in 99.999% uptime semiconductor  
package applications on both ceramic and organic  
substrates. The C4 solder ball termination option is the  
perfect compliment to flip-chip packaging technology.  
Mainframe class CPUs, ultimate performance multi-chip  
modules, and communications systems that must have the  
reliability of 5 9s use LICA®.  
LICA® products with either Sn/Pb or Pb-free solder balls are  
used for decoupling in high reliability military and aerospace  
applications. These LICA® devices are used for decoupling of  
large pin count FPGAs, ASICs, CPUs, and other high power  
ICs with low operating voltages.  
The first family of LGA products are 2 terminal devices. A  
2 terminal 0306 LGA delivers ESL performance that is equal  
to or better than an 0306 8 terminal IDC. The 2 terminal 0805  
LGA delivers ESL performance that approaches the 0508  
8 terminal IDC. New designs that would have used 8 terminal  
IDCs are moving to 2 terminal LGAs because the layout is  
easier for a 2 terminal device and manufacturing yield is better  
for a 2 terminal LGA versus an 8 terminal IDC.  
LGA technology is also used in a 4 terminal family of products  
that AVX is sampling and will formerly introduce in 2008.  
Beyond 2008, there are new multi-terminal LGA product  
families that will provide even more attractive options for PDN  
designers.  
When high reliability decoupling applications require the very  
lowest ESL capacitors, LICA® products are the best option.  
470 nF 0306 Impedance Comparison  
1
0306 2T-LGA  
0306 LICC  
0306 8T-IDC  
0603 MLCC  
0.1  
0.01  
0.001  
1
10  
100  
1000  
Frequency (MHz)  
Figure 2 MLCC, LICC, IDC, and LGA technologies deliver different levels of equivalent series inductance (ESL).  
60  
Low Inductance Capacitors (RoHS)  
0612/0508/0306/0204 LICC (Low Inductance Chip Capacitors)  
GENERAL DESCRIPTION  
The key physical characteristic determining equivalent  
series inductance (ESL) of a capacitor is the size of the  
current loop it creates. The smaller the current loop, the  
lower the ESL.  
A standard surface mount MLCC is rectangular in shape  
with electrical terminations on its shorter sides. A Low  
Inductance Chip Capacitor (LICC) sometimes referred to  
as Reverse Geometry Capacitor (RGC) has its  
terminations on the longer sides of its rectangular shape.  
The image on the right shows the termination differences  
between an MLCC and an LICC.  
LICC  
MLCC  
When the distance between terminations is reduced, the  
size of the current loop is reduced. Since the size of the  
current loop is the primary driver of inductance, an 0306  
with a smaller current loop has significantly lower ESL  
then an 0603. The reduction in ESL varies by EIA size,  
however, ESL is typically reduced 60% or more with an  
LICC versus a standard MLCC.  
PERFORMANCE CHARACTERISTICS  
Capacitance Tolerances K = 10%ꢀ M = 20%  
Operation  
X7R = -55°C to +125°C  
X5R = -55°C to +85°C  
X7S = -55°C to +125°C  
Temperature Range  
AVX LICC products are available with a lead-free finish of  
plated Nickel/Tin.  
Temperature Coefficient X7R, X5R = 15%ꢀ X7S = 22%  
Voltage Ratings  
4, 6.3, 10, 16, 25 VDC  
Dissipation Factor  
4V, 6.3V = 6.5% maxꢀ 10V = 5.0% maxꢀ  
16V = 3.5% maxꢀ 25V = 3.0% max  
Insulation Resistance  
(@+25°C, RVDC)  
100,000MΩ min, or 1,000MΩ per  
μF min.,whichever is less  
HOW TO ORDER  
0612  
Z
D
105  
M
A
T
2
A*  
Size  
0204  
0306  
0508  
0612  
Voltage  
4 = 4V  
6 = 6.3V  
Z = 10V  
Y = 16V  
3 = 25V  
5 = 50V  
Dielectric  
C = X7R  
D = X5R  
W = X6S  
Z = X7S  
Capacitance  
Code (In pF)  
2 Sig. Digits +  
Number of Zeros  
Capacitance  
Tolerance  
K = 10%  
Failure Rate Terminations  
Packaging  
Available  
2 = 7" Reel  
4 = 13" Reel  
Thickness  
Thickness  
mm (in)  
0.35 (0.014)  
0.56 (0.022)  
0.61 (0.024)  
0.76 (0.030)  
1.02 (0.040)  
1.27 (0.050)  
A = N/A  
T = Plated Ni  
and Sn  
M = 20%  
NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers.  
TYPICAL IMPEDANCE CHARACTERISTICS  
10  
1
10  
MLCC_0805  
MLCC_1206  
1
0.1  
0.1  
LICC_0508  
LICC_0612  
0.01  
0.001  
0.01  
0.001  
1
10  
Frequency (MHz)  
100  
1000  
1
10  
100  
1000  
Frequency (MHz)  
61  
Low Inductance Capacitors (RoHS)  
0612/0508/0306/0204 LICC (Low Inductance Chip Capacitors)  
SIZE  
0204  
0306  
0508  
0612  
PHYSICAL DIMENSIONS AND  
PAD LAYOUT  
Packaging  
Embossed  
Embossed  
Embossed  
mm  
0.81 0.15  
(0.032 0.006)  
1.27 0.25  
(0.050 0.010)  
1.60 0.25  
(0.063 0.010)  
Length  
(in.)  
mm  
(in.)  
1.60 0.15  
(0.063 0.006)  
2.00 0.25  
(0.080 0.010)  
3.20 0.25  
(0.126 0.010)  
Width  
t
WVDC  
4
6.3 10 16  
4
6.3 10 16 25 50 6.3 10 16 25 50 6.3 10 16 25 50  
W
CAP 0.001  
(μF)  
0.0022  
T
0.0047  
0.010  
0.015  
0.022  
0.047  
0.068  
0.10  
0.15  
0.22  
0.47  
0.68  
1.0  
L
PHYSICAL CHIP DIMENSIONS mm (in)  
L
W
t
1.60 0.25  
(0.063 0.010)  
3.20 0.25  
(0.126 0.010)  
0.13 min.  
(0.005 min.)  
0612  
0508  
0306  
0204  
1.27 0.25  
(0.050 0.010)  
2.00 0.25  
(0.080 0.010)  
0.13 min.  
(0.005 min.)  
0.81 0.15  
(0.032 0.006)  
1.60 0.15  
(0.063 0.006)  
0.13 min.  
(0.005 min.)  
0.50 0.05  
(0.020 0.002)  
1.00 0.05  
(0.040 0.002)  
0.18 0.08  
(0.007 0.003)  
1.5  
T - See Range Chart for Thickness and Codes  
2.2  
3.3  
PAD LAYOUT DIMENSIONS  
mm (in)  
4.7  
A
B
C
10  
0612  
0508  
0306  
0204  
0.76 (0.030)  
0.51 (0.020)  
0.31 (0.012)  
3.05 (0.120)  
2.03 (0.080)  
1.52 (0.060)  
.635 (0.025)  
0.51 (0.020)  
0.51 (0.020)  
Solid = X7R  
= X6S  
= X5R  
= X7S  
mm (in.)  
mm (in.)  
mm (in.)  
mm (in.)  
0306  
0204  
0508  
0612  
Code Thickness  
0.61 (0.024)  
Code Thickness  
Code Thickness  
Code Thickness  
A
C
0.35 (0.014)  
S
V
A
0.56 (0.022)  
0.76 (0.030)  
1.02 (0.040)  
S
V
0.56 (0.022)  
0.76 (0.030)  
1.02 (0.040)  
1.27 (0.050)  
W
A
“B”  
C
“A”  
C
62  

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